Semiconductor storage device

ABSTRACT

A semiconductor integrated circuit device, includes a first and a second bus line making a bus line pair, and a plurality of circuit units, each of the circuit units including, a first transistor, a second transistor, and a third and a fourth transistor sharing a source or a drain. The circuit units includes a first and a second circuit unit arranged in a first direction. One of a source and a drain of the first transistor of the first circuit unit and one of a source and a drain of the second transistor of the first circuit unit are coupled to the first bus line. The source or the drain shared by the third and the fourth transistor of the first circuit unit is coupled to the second bus line.

The present application is a Continuation application of U.S. patentapplication Ser. No. 13/437,783, filed on Apr. 2, 2012, which is basedon and claims priority from Japanese Patent Application No. 2011-087971,filed on Apr. 12, 2011, the entire contents of which are incorporationherein by reference.

BACKGROUND

The present invention relates to a semiconductor storage device, andmore particularly to a dynamic semiconductor storage device.

In the dynamic semiconductor storage device, a reduction in circuit areais an important task. As a method of reducing the circuit area, therehas been known a technique in which a coupling destination diffusionlayer having a switch that column-selects signals output from senseamplifiers of a folding bit line system is shared by repetition of anarray structure.

FIG. 1 is a layout diagram illustrating a semiconductor layout of openbit sense amplifiers in a general semiconductor memory device. Thesemiconductor layout of the sense amplifiers in FIG. 1 will bedescribed.

The layout diagram of FIG. 1 illustrates first to fourth senseamplifiers SA1 to SA4, first to fourth bit lines BL1 to BL4, first tofourth dummy bit lines DBL1 to DBL4, first and second word lines WL1 andWL2, first and second dummy word lines DWL1 and DWL2, first to eighthmemory cells MC1 to MC8, and first to eighth dummy cells DC1 to DC8.

In a lateral direction of FIG. 1, the first to fourth bit lines BL1 toBL4 and the first to fourth dummy bit lines DBL1 to DBL4 are arranged inparallel. In this example, the first dummy bit line DBL1 is arranged onan extension of the first bit line BL1. Likewise, the second to fourthdummy bit lines DBL2 to DBL4 are arranged on extensions of the second tofourth bit lines BL2 to BL4, respectively.

In a direction orthogonal to the first to fourth bit lines BL1 to BL4and the first to fourth dummy bit lines DBL1 to DBL4, that is, in alongitudinal direction of FIG. 1, the first and second word lines WL1and WL2, and the first and second dummy word lines DWL1 and DWL2 arearranged in parallel.

The first to fourth sense amplifiers SA1 to SA4 are arranged in a matrixbetween the first and second word lines WL1 and WL2, and the first andsecond dummy word lines DWL1 and DWL2. That is, the first and secondsense amplifiers SA1 and SA2 are arranged on extensions of the first andsecond bit lines BL1 and BL2, and the first and second dummy bit linesDBL1 and DBL2, so as to be adjacent to each other in a direction of theextension. Likewise, the third and fourth sense amplifiers SA3 and SA4are arranged on extensions of the third and fourth bit lines BL3 andBL4, and the third and fourth dummy bit lines DBL3 and DBL4, so as to beadjacent to each other in a direction of the extension. The first tothird sense amplifiers SA1 and SA3 are arranged adjacent to each otherin a direction of the first and second word lines WL1 and WL2. Likewise,the second and fourth sense amplifiers SA2 and SA4 are arranged adjacentto each other in a direction of the first and second word lines WL1 andWL2.

The first to eighth memory cells MC1 to MC8 are arranged in a matrix atintersections of the first to fourth bit lines BL1 to BL4, and the firstand second word lines WL1 and WL2. In this example, the first to fourthmemory cells MC1 to MC4 are arranged at the intersections of the firstword line WL1, and the first to fourth bit lines BL1 to BL4,respectively. Also, the fifth to eighth memory cells MC5 to MC8 arearranged at the intersections of the second word line WL2, and the firstto fourth bit lines BL1 to BL4, respectively.

Likewise, the first to eighth dummy cells DC1 to DC8 are arranged in amatrix at intersections of the first to fourth dummy bit lines DBL1 toDBL4, and the first and second dummy word lines DWL1 and DWL2. In thisexample, the first to fourth dummy cells DC1 to DC4 are arranged at theintersections of the first dummy word line DWL1, and the first to fourthdummy bit lines DBL1 to DBL4, respectively. Also, the fifth to eighthdummy cells DC5 to DC8 are arranged at the intersections of the seconddummy word line DWL2, and the first to fourth dummy bit lines

The first sense amplifier SA1 has one end coupled to the first bit lineBL1, and the other end coupled to the first dummy bit line DBL1.Likewise, the second to fourth sense amplifiers SA2 to SA4 have one endscoupled to the second to fourth bit lines BL2 to BL4, and the other endscoupled to the second to fourth dummy bit lines DBL2 to DBL4,respectively.

The first word line WL1 is coupled to the first to fourth memory cellsMC1 to MC4. The second word line WL2 is coupled to the fifth to eighthmemory cells MC5 to MC8. Likewise, the first dummy word line DWL1 iscoupled to the first to fourth dummy cells DC1 to DC4. The second dummyword line DWL2 is coupled to the fifth to eighth dummy cells DC5 to DC8.

The first bit line BL1 is coupled to the first and fifth memory cellsMC1 and MC5. The second bit line BL2 is coupled to the second and sixthmemory cells MC2 and MC6. The third bit line BL3 is coupled to the thirdand seventh memory cells MC3 and MC7. The fourth bit line BL4 is coupledto the fourth and eighth memory cells MC4 and MC8.

Likewise, the first dummy bit line DBL1 is coupled to the first andfifth dummy cells DC1 and DC5. The second dummy bit line DBL2 is coupledto the second and sixth dummy cells DC2 and DC6. The third dummy bitline DBL3 is coupled to the third and seventh dummy cells DC3 and DC7.The fourth dummy bit line DBL4 is coupled to the fourth and eighth dummycells DC4 and DC8.

The first to fourth bit lines BL1 to BL4 communicate information chargewith the first to eighth memory cells MC1 to MC8. Likewise, the first tofourth dummy bit lines DBL1 to DBL4 communicate information charge withthe first to eighth dummy cells DC1 to DC8.

Any one of the first and second word lines WL1 and WL2 is selected toconduct the selection of the first to eighth memory cells MC1 to MC8. Inthis situation, likewise, any one of the first and second dummy wordlines DWL1 and DWL2 is selected to conduct the selection of the first toeighth dummy cells DC1 to DC8.

In this example, any memory cell is arranged at all of the intersectionsbetween the first to fourth bit lines BL1 to BL4, and the first andsecond word lines WL1 and WL2. Likewise, any dummy cell is arranged atall of the intersections of the first to fourth dummy bit lines DBL1 toDBL4, and the first and second dummy word lines DWL1 and DWL2. That is,a configuration of the bit lines corresponding to the cell array is ofan open type.

Each of the first to eighth memory cells MC1 to MC8 is configured by onetransistor and one capacitor. Each of those memory cells stores binarydata of one bit as charging and discharging states of the capacitortherein, and inputs and outputs the data through the transistor selectedby the bit line and the word line coupled to two terminals thereof.

FIG. 3 is a block diagram illustrating wiring for a BUS signal, a dummybus signal, and a column select signal in the sense amplifiers in asimplified layout diagram of FIG. 1. The block diagram of FIG. 3illustrates a first memory cell array MCA1, a second memory cell arrayMCA2, a first sense amplifier circuit SA1, a second sense amplifiercircuit SA2, a first bit line BL1, a second bit line BL2, a first dummybit line DBL1, a second dummy bit line DBL2, a first column selectsignal line YSW1, a second column select signal line YSW2, a bus lineBUS1, and a dummy bus line DBUS1.

In the block diagram of FIG. 3, the first memory cell array MCA1corresponds to the first, second, fifth, and sixth memory cells MC1,MC2, MC5, and MC6 in FIG. 1. The second memory cell array MCA2corresponds to the first, second, fifth, and sixth dummy cells DC1, DC2,DC5, and DC6 in FIG. 1. The first sense amplifier circuit SA1, thesecond sense amplifier circuit SA2, the first bit line BL1, the secondbit line BL2, the first dummy bit line DBL1, and the second dummy bitline DBL2 are denoted by the same symbols in FIGS. 1 and 2.

FIG. 2 is a circuit block diagram schematically illustrating an internalconfiguration of the first sense amplifier circuit SA1 in FIG. 3.Referring to FIG. 2, the first sense amplifier circuit SA1 includes asense amplifier SA, an equalizer circuit EQ, and a transfer circuit DQ.The transfer circuit DQ includes a first transistor DQT1 and a secondtransistor DQT2.

The first column select signal line YSW1 is coupled to the first senseamplifier circuit SA1. Similarly, the second column select signal lineYSW2 is coupled to the second sense amplifier circuit SA2 (not shown inFIG. 2). The first bit line BL1 and the first dummy bit line DBL1 arecoupled to the first sense amplifier circuit SA1. The second bit lineBL2 and the second dummy bit line DBL2 are coupled to the second senseamplifier circuit SA2.

In the first sense amplifier circuit SA1 of FIG. 2, the first bit lineBL1 is commonly coupled to one end of the sense amplifier SA, one end ofthe equalizer circuit EQ, and one of a source and a drain of the firsttransistor DQT1 in the transfer circuit DQ. The first dummy bit lineDBL1 is commonly coupled to the other end of the sense amplifier SA, theother end of the equalizer circuit EQ, and one of a source and a drainof the second transistor DQT2. The bus line BUS1 is coupled to the otherof the source and the drain of the first transistor DQT1. The dummy busline DBUS1 is coupled to the other of the source and the drain of thesecond transistor DQT2 in the transfer circuit DQ. The first columnselect signal line YSW1 is commonly coupled to gates of the first andsecond transistors DQT1 and DQT2 in the transfer circuit DQ.

Referring to FIGS. 2 and 3, the operation of the sense amplifier circuitin a related art will be described. First, the sense amplifier SAdetermines values of the respective signals that are transmitted throughthe first bit line BL1 and the first dummy bit line DBL1. Then, thefirst column select signal line YSW1 transmits the respective signalsdecided by the first bit line BL1 and the first dummy bit line DBL1toward an external circuit through the bus line BUS1 and the dummy busline DBUS1. Thereafter, the signals transmitted through the bus lineBUS1 and the dummy bus line DBUS1 are amplified by a downstream circuit.Accordingly, a difference in signal capacity between the bus line BUS1and the dummy bus line DBUS1 needs to be reduced as much as possible.This is because the large difference in the signal capacity may cause amalfunction or a speed delay in the downstream circuit.

FIG. 4A is a circuit diagram illustrating a portion relating to thefirst to fourth transfer circuits DQ1 to DQ4 in the first to fourthsense amplifiers SA1 to SA4, extracted from the semiconductor memorydevice of FIG. 1. The circuit diagram of FIG. 4A includes first tofourth transfer circuits DQ1 to DQ4, first to fourth column selectsignal lines YSW1 to YSW4, the first to fourth bit lines BL1 to BL4, thefirst to fourth dummy bit lines DBL1 to DBL4, the bus line BUS1, and thedummy bus line DBUS1. The first transfer circuit DQ1 includes a firsttransistor DQ1T1 and a second transistor DQ1T2. The second transfercircuit DQ2 includes a first transistor DQ2T1 and a second transistorDQ2T2. The third transfer circuit DQ3 includes a first transistor DQ3T1and a second transistor DQ3T2. The fourth transfer circuit DQ4 includesa first transistor DQ4T1 and a second transistor DQ4T2.

The first column select signal line YSW1 is commonly coupled to therespective gates of the first and second transistors DQ1T1 and DQ1T2 inthe first transfer circuit DQ1. The first bit line BL1 is coupled to oneof a source and a drain of the first transistor DQ1T1 in the firsttransfer circuit DQ1. The first dummy bit line DBL1 is coupled to one ofa source and a drain of the second transistor DQ1T2 in the firsttransfer circuit DQ1.

Likewise, when an index i is generalized as any one of integers 2 to 4,an i-th column select signal line YSWi is commonly coupled to therespective gates of first and second transistors DQiT1 and DQiT2 in ani-th transfer circuit DQi. An i-th bit line BLi is coupled to one of asource and a drain of the first transistor DQiT1 in the i-th transfercircuit DQi. An i-th dummy bit line DBLi is coupled to one of a sourceand a drain of the second transistor DQiT2 in the i-th transfer circuitDQi.

The bus line BUS1 is commonly coupled to the other of the source and thedrain of the respective first transistors DQ1T1 to DQ4T1 in the first tofourth transfer circuits DQ1 to DQ4. The dummy bus line DBUS1 iscommonly coupled to the other of the source and the drain of therespective second transistors DQ1T2 to DQ4T2 in the respective first tofourth transfer circuits DQ1 to DQ4.

FIG. 4B is a plan view illustrating a semiconductor layout according tothe circuit diagram of FIG. 4A. Each of the first and second transistorsDQ1T1 to DQ4T1 and DQ1T2 to DQ4T2 in the respective first to fourthtransfer circuits DQ1 to DQ4 is drawn as a diffusion layer and a gateformed on the diffusion layer. In this example, portions of thediffusion layer on both sides of the gate in each transistor operate asthe source and the drain. Also, the first to fourth column select signallines YSW1 to YSW4 are drawn as wires that couple the gates of the twotransistors.

FIG. 4C is a plan view illustrating a semiconductor layout in which thesemiconductor layout of FIG. 4B is improved to share the diffusionlayers of partial transistors. The semiconductor layout of FIG. 4C isequivalent to the semiconductor layout of FIG. 4B which is modified asfollows. That is, a positional relationship of the first and secondtransistors DQ1T1 and DQ1T2 in the first transfer circuit DQ1 is firsthorizontally reversed. Further, a positional relationship of the sourceand the drain of each of the first and second transistors DQ1T1 andDQ1T2 in the first transfer circuit DQ1 is horizontally reversed. Then,the diffusion layer of one of the source and the drain of the firsttransistor DQ1T1 in the first transfer circuit DQ1, which is coupled tothe bus line BUS1, and the diffusion layer of one of the source and thedrain of the first transistor DQ2T1 in the second transfer circuit DQ2,which is coupled to the bus line BUS1, are integrated with each other.As a result, the first transistor DQ1T1 in the first transfer circuitDQ1 and the first transistor DQ2T1 in the second transfer circuit DQ2are configured so that two gates are formed in one diffusion layer.

Likewise, a positional relationship of the first and second transistorsDQ3T1 and DQ3T2 in the third transfer circuit DQ3 is first horizontallyreversed. Further, a positional relationship of the source and the drainof each of the first and second transistors DQ3T1 and DQ3T2 in the thirdtransfer circuit DQ3 is horizontally reversed. Then, the diffusion layerof one of the source and the drain of the first transistor DQ3T1 in thethird transfer circuit DQ3, which is coupled to the bus line BUS1, andthe diffusion layer of one of the source and the drain of the firsttransistor DQ4T1 in the fourth transfer circuit DQ4, which is coupled tothe bus line BUS1, are integrated with each other. As a result, thefirst transistor DQ3T1 in the third transfer circuit DQ3 and the firsttransistor DQ4T1 in the fourth transfer circuit DQ4 are configured sothat two gates are formed in one diffusion layer.

The semiconductor layout of FIG. 4C obtained by improving thesemiconductor layout of FIG. 4B as described above is reduced indimension in the lateral direction of the drawing so that a circuit areacan be saved. On the other hand, there arises such a problem that adifference in capacity between the bus line BUS1 and the dummy bus lineDBUS1 is increased as with a total area of the diffusion layers coupledwith the respective lines.

In association with the above description, Japanese Unexamined PatentApplication Publication No. Hei 7(1995)-254650 discloses a techniquepertaining to a dynamic semiconductor storage device. The dynamicsemiconductor storage device in Japanese Unexamined Patent ApplicationPublication No. Hei 7(1995)-254650 includes a plurality of dynamicmemory cells, a plurality of bit lines, a plurality of word lines, andsense amplifier blocks. In this configuration, the dynamic memory cellsare arranged two-dimensionally. The bit lines communicate informationwith those memory cells. The word lines are arranged across those bitlines, and select the memory cells for extracting the information to thebit lines. In each of the sense amplifier blocks are arranged the senseamplifier coupled to the bit line and an equalizer circuit thatequalizes the bit line in order to detect and amplify the information inthe memory cell, which is extracted to the bit line. In the dynamicsemiconductor storage device, a plurality of the sense amplifier blocksis arranged adjacent to each other in a direction of the bit lines. Thebit line having another sense amplifier block existing between the bitline and a given sense amplifier block to be coupled is coupled with awiring layer different from the wiring layer configuring the bit lines.This wiring layer passes through the another sense amplifier, and iscoupled to the given sense amplifier block.

Also, Japanese Patent No. 3004177 discloses a technique pertaining to asemiconductor integrated circuit device. The semiconductor integratedcircuit device of Japanese Patent No. 3004177 includes column gates eachhaving a first circuit element, and sense circuits each having a secondcircuit element. In this example, the first and second circuit elementsare integrated in the same pattern with each other. In the semiconductorintegrated circuit device, each of the column gates includes at least afirst transistor disposed in an element area of a semiconductorsubstrate as the first circuit element. Each of the sense circuitsincludes at least a second transistor having a common node with thefirst transistor disposed in the element area as the second circuitelement.

Also, Japanese Unexamined Patent Application Publication No. 2004-348934discloses a technique pertaining to the memory cell. The memory cell ofJapanese Unexamined Patent Application Publication No. 2004-348934includes a first transistor, and a magnetoresistive element. In thisexample, the first transistor includes a first gate, a first terminal asone terminal thereof other than the first gate, and a second terminal asthe other terminal thereof. The magnetoresistive element has aspontaneous magnetization whose magnetization direction is reversedaccording to stored data, and includes a third terminal as one terminalthereof, and a fourth terminal as the other terminal thereof. The firstterminal is coupled to the first bit line. The second terminal iscoupled to the second bit line. The first gate is coupled to the firstword line. The third terminal is coupled to the second work line. Thefourth terminal is coupled to the second terminal.

SUMMARY

When the diffusion layers of the column select transistors extractedfrom the sense amplifiers to the bus lines are shared in the relatedart, the capacities among the complemented bus lines are unbalanceddepending on a difference in the capacity among the diffusion layers ofthe column select transistors coupled to a bus line T/B (true/bar). As aresult, during read operation for reading information in the memorycell, since bus drive from the bit line is conducted by analog operationof a small amplitude, there is a possibility that malfunction occurs inthe amplifying operation of the bus line due to the above-mentionedunbalanced capacities when amplifying the bus line. Therefore, there isa need to equalize the diffusion layer capacities of the selecttransistors which are parasitic in the complemented bus line.

Hereinafter, a description will be given of a solution to problem byusing reference numerals used in “Detailed Description”. Those referencenumerals are referred for the purpose of clarifying correspondencerelationships between the definitions in “What is claimed is” and“Detailed Description”. However, those reference numerals must not beused for interruption of technical scopes of the present invention,which are defined in “What is claimed is”.

According to an aspect of the present invention, the semiconductorintegrated circuit device includes a wiring pair ((BUS1, DBUS1), a firsttransistor group (DQiT1), a second transistor group (DQiT2), a firstdiffusion layer group, and a second diffusion layer group. In thisexample, the first transistor group (DQiT1) has a source or a draincoupled with one (BUS1) of the wiring pair. The second transistor group(DQiT2) has a source or a drain coupled with the other (DBUS1) of thewiring pair. The first diffusion layer group is formed with the firsttransistor group (DQiT1). The second diffusion layer group is formedwith the second transistor group (DQiT2). The first diffusion layergroup is equipped with a first common diffusion layer group. In thisexample, the first common diffusion layer group includes the firsttransistor group (DQiT1), and is also formed with a plurality oftransistors (DQiT1) sharing the source or the drain. The seconddiffusion layer group is equipped with a second common diffusion layergroup. In this example, the second common diffusion layer group includesthe second transistor group (DQiT2), and is also formed with a pluralityof transistors (DQiT2) sharing the source or the drain. The firstcapacitive load of the one (BUS1) of the wiring pair is balanced withthe second capacitive load of the other (DBUS1) of the wiring pair.

According to another aspect of the present invention, the semiconductorstorage device includes a wiring pair (BUS1, DBUS1), a first block (forexample, DQ1T1 to DQ4T1 and DQ1T2 to DQ4T2, etc.), and a second block(for example, DQ5T1 to DQ8T1 and DQ5T2 to DQ8T2, etc.). In this example,the first block (for example, DQ1T1 to DQ4T1 and DQ1T2 to DQ4T2, etc.)includes a plurality of elements (for example, DQ1T1 and DQ2T1) which iscoupled to any one (for example, BUS1) of the wiring pair (BUS1, DBUS1)through the first wiring. The second block (for example, DQ5T1 to DQ8T1and DQ5T2 to DQ8T2, etc.) includes a plurality of elements which iscoupled to any one of the wiring pair (BUS1, DBUS1) through the secondwiring. The second block is arranged adjacent to the first block. Theplurality of elements in the second block is identical with theplurality of elements in the first block. The number of first wiringscoupled to one of the wiring pair is different from the number of secondwirings.

According to the aspects of the present invention, the semiconductorstorage device of the present invention, the diffusion layer groupswhich are the coupling destinations of the pair (T/B) of the bus linescoupled to the column select switch are alternately arranged orstaggered. As a result, a distribution of the diffusion layer capacitiesin the bus line pair flattened at the time of amplifying thecolumn-selected signal. Accordingly, the amplifying operation stable inthe column-selected signal can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout diagram illustrating a semiconductor layout of anopen bit sense amplifier in a general semiconductor memory device;

FIG. 2 is a block diagram illustrating wirings relating to a BUS signal,a dummy bus signal, and a column select signal in the sense amplifier ina simplified layout diagram of FIG. 1;

FIG. 3 is a block circuit diagram schematically illustrating an internalconfiguration of a first sense amplifier circuit in FIG. 2;

FIG. 4A is a circuit diagram illustrating a portion relating to first tofourth transfer circuits in first to fourth sense amplifier circuitsextracted from the semiconductor memory device of FIG. 1;

FIG. 4B is a plan view illustrating a semiconductor layout according tothe circuit diagram of FIG. 4A;

FIG. 4C is a plan view illustrating a semiconductor layout in which thesemiconductor layout of FIG. 4B is improved by commondizing diffusionlayers of partial transistors;

FIG. 5A is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a first embodimentof the present invention;

FIG. 5B is a circuit diagram illustrating a configuration of a circuitrealized by the semiconductor layout of FIG. 5A;

FIG. 6 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a second embodimentof the present invention;

FIG. 7 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a third embodimentof the present invention;

FIG. 8 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a fourth embodimentof the present invention;

FIG. 9 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a fifth embodimentof the present invention; and

FIG. 10 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a sixth embodimentof the present invention.

DETAILED DESCRIPTION

Modes for carrying out a semiconductor integrated circuit deviceaccording to the present invention will be described below withreference to the accompanying drawings.

First Embodiment

FIG. 5A is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a first embodimentof the present invention. FIG. 5B is a circuit diagram illustrating aconfiguration of a circuit realized by the semiconductor layout of FIG.5A. First, the circuit diagram of FIG. 5B will be described.

The circuit diagram of FIG. 5B is equivalent to the combination of twoof the circuit diagrams of FIG. 4A described as the related art. Aconfiguration element in the circuit diagram of FIG. 5B will bedescribed. The circuit of FIG. 5B includes first to eighth transfercircuits DQ1 to DQ8, first to eighth column select signal lines YSW1 toYSW8, a bus line BUS1, a dummy bus line DBUS1, first to fourth bit linesBL1 to BL4, and first to fourth dummy bit lines DBL1 to DBL4.

The first transfer circuit DQ1 includes a first transistor DQ1T1 and asecond transistor DQ1T2. Likewise, the second to eighth transfercircuits DQ2 to DQ8 also include the first transistors DQ2T1 to DQ8T1,and the second transistors DQ8T1 to DQ8T2, respectively.

A coupling relationship of the constituent elements in the circuit ofFIG. 5B will be described. The first column select signal line YSW1 iscommonly coupled to gates of the first and second transistors DQ1T1 andDQ1T2 in the first transfer circuit DQ1. One of a source and a drain ofthe first transistor DQ1T1 in the first transfer circuit DQ1 is coupledto the first bit line BL1. The other of the source and the drain of thefirst transistor DQ1T1 in the first transfer circuit DQ1 is coupled tothe first bus line BUS1. One of a source and a drain of the secondtransistor DQ1T2 in the first transfer circuit DQ1 is coupled to thefirst dummy bit line DBL1. The other of the source and the drain of thesecond transistor DQ1T2 in the first transfer circuit DQ1 is coupled tothe first dummy bus line DBUS1.

Likewise, the second to eighth column select signal lines YSW2 to YSW8are commonly coupled to gates of the first and second transistors DQ2T1to DQ8T1 and DQ2T2 to DQ8T2 in the second to eighth transfer circuitsDQ2 to DQ8, respectively. One of sources and drains of the firsttransistors DQ2T1 to DQ8T1 in the second to eighth transfer circuits DQ2to DQ8 is coupled to the second to fourth bit lines BL2 to BL4,respectively. The other of the sources and the drains of the firsttransistors DQ2T1 to DQ8T1 in the second to eighth transfer circuits DQ2to DQ8 is coupled to the bus line BUS1, respectively. One of a sourceand a drain of the second transistors DQ2T2 to DQ8T2 in the second toeighth transfer circuits DQ2 to DQ8 is coupled to the second to eighthdummy bit lines DBL2 to DBL4, respectively. The other of the source andthe drain of the second transistors DQ2T2 to DQ8T2 in the second toeighth transfer circuits DQ2 to DQ8 is coupled to the first dummy busline DBUS1, respectively.

Subsequently, the plan view of FIG. 5A will be described. The plan viewof FIG. 5A illustrates the semiconductor layout corresponding to thecircuit of FIG. 5B, and also illustrates first to fourth memory cellarrays MCA1 to MCA4.

The constituent elements of the semiconductor layout corresponding tothe circuit of FIG. 5B, which are illustrated in FIG. 5A will bedescribed. The semiconductor layout of FIG. 5A includes first to eighthdiffusion layers DL1 to DL8, first to fourth common diffusion layersCDL1 to CDL4, the first to eighth column select signal lines YSW1 toYSW8, the bus line BUS1, the dummy bus line DBUS1, the first to fourthbit lines BL1 to BL4, and the first to fourth dummy bit lines DBL1 toDBL4.

The first diffusion layer DL1 is formed with the second transistor DQ1T2in the first transfer circuit DQ1. In FIG. 5A, a gate portion of thesecond transistor DQ1T2 is indicated as the second transistor DQ1T2 inthe first transfer circuit DQ1. Areas of the first diffusion layer DL1at right and left ends thereof, which are expanded at both sides of thegate portion function as the source and the drain of the secondtransistor DQ1T2 in the first transfer circuit DQ1.

Likewise, the second to fourth diffusion layers DL2 to DL4 are formedwith the second transistors DQ2T2 to DQ4T2 in the second to fourthtransfer circuits DQ2 to DQ4, respectively. In FIG. 5A, gate portions ofthe second transistors DQ2T2 to DQ2T4 are indicated as the secondtransistors DQ1T2 to DQ2T4 in the second to fourth transfer circuits DQ2to DQ4, respectively. Areas of the second to fourth diffusion layers DL2to DL4 at right and left ends thereof, which are expanded at both sidesof the gate portions function as the sources and the drains of thesecond transistors DQ2T2 to DQ4T2 in the second to fourth transfercircuits DQ2 to DQ4, respectively.

Also, the fifth diffusion layer DL5 is formed with the first transistorDQ5T1 in the fifth transfer circuit DQ5. In FIG. 5A, a gate portion ofthe first transistor DQ5T1 is indicated as the first transistor DQ5T1 inthe fifth transfer circuit DQ5. Areas of the fifth diffusion layer DL5at right and left ends thereof, which are expanded at both sides of thegate portion function as the source and the drain of the firsttransistor DQ5T1 in the fifth transfer circuit DQ5.

Likewise, the sixth to eighth diffusion layers DL6 to DL8 are formedwith the first transistors DQ6T1 to DQ8T1 in the sixth to eighthtransfer circuits DQ6 to DQ8, respectively. In FIG. 5A, gate portions ofthe first transistors DQ6T1 to DQ8T1 are indicated as the firsttransistors DQ6T1 to DQ8T1 in the sixth to eighth transfer circuits DQ6to DQ8, respectively. Areas of the sixth to eighth diffusion layers DL6to DL8 at right and left ends thereof, which are expanded at both sidesof those gate portions function as the sources and the drains of thefirst transistors DQ6T1 to DQ8T1 in the sixth to eighth transfercircuits DQ6 to DQ8, respectively.

The first transistors DQ1T1 and DQ2T1 in the first and second transfercircuits DQ1 and DQ2 are formed on the left side and the right side ofthe first common diffusion layer CDL1, respectively. In FIG. 5A, as thefirst transistors DQ1T1 and DQ2T1 in the first and second transfercircuits DQ1 and DQ2, the respective gate portions formed on left andright are indicated. The first common diffusion layer CDL1 is dividedinto three pieces by those left and right gate portions. The left areaof the first common diffusion layer CDL1 in FIG. 5A is coupled with thefirst bit line BL1, and this area represents one of the source and thedrain of the first transistor DQ1T1 in the first transfer circuit DQ1,which is described in FIG. 5B. The right area of the first commondiffusion layer CDL1 in FIG. 5A is coupled with the first bit line BL2,and this area represents one of the source and the drain of the firsttransistor DQ2T1 in the first transfer circuit DQ2, which is describedin FIG. 5B. A center area of the first common diffusion layer CDL1interposed between those gate portions is coupled with the first busline BUST. The center area functions as the other of the source and thedrain of the first transistor DQ1T1 in the first transfer circuit DQ1,which is described with reference to FIG. 5B while functioning as theother of the source and the drain of the first transistor DQ2T1 in thesecond transfer circuit DQ2. That is, the center area interposed betweenthose two gate portions represents the source or the drain shared by thefirst transistors DQ1T1 and DQ2T1 in the first and second transfercircuits DQ1 and DQ2.

Likewise, the first transistors DQ3T1 and DQ4T1 in the third and fourthtransfer circuits DQ3 and DQ4 are formed on the left side and the rightside of the second common diffusion layer CDL2, respectively. In FIG.5A, as the first transistors DQ3T1 and DQ4T1 in the third and fourthtransfer circuits DQ3 and DQ4, the respective gate portions formed onleft and right are indicated. The second common diffusion layer CDL2 isdivided into three pieces by those left and right gate portions. Theleft area of the second common diffusion layer CDL2 in FIG. 5A iscoupled with the third bit line BL3, and this area represents one of thesource and the drain of the first transistor DQ3T1 in the third transfercircuit DQ3, which is described in FIG. 5B. The right area of the secondcommon diffusion layer CDL2 in FIG. 5A is coupled with the fourth bitline BL4, and this area represents one of the source and the drain ofthe first transistor DQ4T1 in the fourth transfer circuit DQ4, which isdescribed in FIG. 5B. A center area of the second common diffusion layerCDL2 interposed between those gate portions is coupled with the bus lineBUS1. The center area functions as the other of the source and the drainof the first transistor DQ3T1 in the third transfer circuit DQ3, whichis described with reference to FIG. 5B while functioning as the other ofthe source and the drain of the first transistor DQ4T1 in the fourthtransfer circuit DQ4. That is, the center area interposed between thosetwo gate portions represents the source or the drain shared by the firsttransistors DQ3T1 and DQ4T1 in the third and fourth transfer circuitsDQ3 and DQ4.

Also, the second transistors DQ5T2 and DQ6T2 in the fifth and sixthtransfer circuits DQ5 and DQ6 are formed on the left side and the rightside of the third common diffusion layer CDL3, respectively. In FIG. 5A,as the second transistors DQ5T2 and DQ6T2 in the fifth and sixthtransfer circuits DQ5 and DQ6, the respective gate portions formed onleft and right are indicated. The third common diffusion layer CDL3 isdivided into three pieces by those left and right gate portions. Theleft area of the third common diffusion layer CDL3 in FIG. 5A is coupledwith the first dummy bit line DBL1, and this area represents one of thesource and the drain of the second transistor DQ5T2 in the fifthtransfer circuit DQ5, which is described in FIG. 5B. The right area ofthe third common diffusion layer CDL3 in FIG. 5A is coupled with thesecond dummy bit line DBL2, and this area represents one of the sourceand the drain of the second transistor DQ6T2 in the sixth transfercircuit DQ6, which is described in FIG. 5B. A center area of the thirdcommon diffusion layer CDL3 interposed between those gate portions iscoupled with the dummy bus line DBUS1. The center area functions as theother of the source and the drain of the second transistor DQ5T2 in thefifth transfer circuit DQ5, which is described with reference to FIG. 5Bwhile functioning as the other of the source and the drain of the secondtransistor DQ6T2 in the sixth transfer circuit DQ6. That is, the centerarea interposed between those two gate portions represents the source orthe drain shared by the second transistors DQ5T2 and DQ6T2 in the fifthand sixth transfer circuits DQ5 and DQ6.

Likewise, the second transistors DQ7T2 and DQ8T2 in the seventh andeighth transfer circuits DQ7 and DQ8 are formed on the left side and theright side of the fourth common diffusion layer CDL4, respectively. InFIG. 5A, as the second transistors DQ7T2 and DQ8T2 in the seventh andeighth transfer circuits DQ7 and DQ8, the respective gate portionsformed on left and right are indicated. The fourth common diffusionlayer CDL4 is divided into three pieces by those left and right gateportions. The left area of the fourth common diffusion layer CDL4 inFIG. 5A is coupled with the third dummy bit line DBL3, and this arearepresents one of the source and the drain of the second transistorDQ7T2 in the seventh transfer circuit DQ7, which is described in FIG.5B. The right area of the fourth common diffusion layer CDL4 in FIG. 5Ais coupled with the fourth dummy bit line DBL4, and this area representsone of the source and the drain of the second transistor DQ8T2 in theeighth transfer circuit DQ8, which is described in FIG. 5B. A centerarea of the fourth common diffusion layer CDL4 interposed between thosegate portions is coupled with the dummy bus line DBUS1. The center areafunctions as the other of the source and the drain of the secondtransistor DQ7T2 in the seventh transfer circuit DQ7, which is describedwith reference to FIG. 5B while functioning as the other of the sourceand the drain of the second transistor DQ8T2 in the eighth transfercircuit DQ8. That is, the center area interposed between those two gateportions represents the source or the drain shared by the secondtransistors DQ7T2 and DQ8T2 in the seventh and eighth transfer circuitsDQ7 and DQ8.

Thus, the two diffusion layers used in the related art illustrated inFIG. 4B are replaced with the common diffusion layer illustrated in FIG.5A, thereby enabling the circuit area to be saved. That is, in theexample of FIG. 5A, the circuit area can be saved by twice the width ofthe source or the drain in the transfer circuit, and twice a distancebetween the diffusion layers.

A description will be given of the positional relationships and couplingrelationships of the constituent elements in the semiconductor layout ofFIG. 5A. The first common diffusion layer CDL1 is arranged between thefirst and second diffusion layers DL1 and DL2 in the lateral directionof FIG. 5A. Likewise, the second common diffusion layer CDL2 is arrangedbetween the third and fourth diffusion layers DL3 and DL4 in the lateraldirection of FIG. 5A. A first block having the first diffusion layerDL1, the first common diffusion layer CDL1, and the second diffusionlayer DL2, and a second block having the third diffusion layer DL3, thesecond common diffusion layer CDL1, and the fourth diffusion layer DL4are aligned in the longitudinal direction of FIG. 5A. The first blockand the second block are arranged between the first and second memorycell arrays MCA1 and MCA2 in the lateral direction of FIG. 5A.

The third common diffusion layer CDL3 is arranged between the fifth andsixth diffusion layers DL5 and DL6 in the lateral direction of FIG. 5A.Likewise, the fourth common diffusion layer CDL4 is arranged between theseventh and eighth diffusion layers DL7 and DL8 in the lateral directionof FIG. 5A. A third block having the fifth diffusion layer DL5, thethird common diffusion layer CDL3, and the sixth diffusion layer DL6,and a fourth block having the seventh diffusion layer DL7, the fourthcommon diffusion layer CDL4, and the eighth diffusion layer DL8 arealigned in the longitudinal direction of FIG. 5A. The third block andthe fourth block are arranged between the third and fourth memory cellarrays MCA3 and MCA4 in the lateral direction of FIG. 5A.

In other words, when attention is paid to the first and third commondiffusion layers CDL1 and CDL3, the first memory cell array MCA1, thefirst diffusion layer DL1, the first common diffusion layer CDL1, thesecond diffusion layer DL2, the second memory cell array MCA2, the thirdmemory cell array MCA3, the fifth diffusion layer DL5, the third commondiffusion layer CDL3, the sixth diffusion layer DL6, and the fourthmemory cell array MCA4 are aligned in the stated order in one direction.Likewise, when attention is paid to the second and fourth commondiffusion layers CDL2 and CDL4, the first memory cell array MCA1, thethird diffusion layer DL3, the second common diffusion layer CDL2, thefourth diffusion layer DL4, the second memory cell array MCA2, the thirdmemory cell array MCA3, the seventh diffusion layer DL7, the fourthcommon diffusion layer CDL4, the eighth diffusion layer DL8, and thefourth memory cell array MCA4 are aligned in the stated order in onedirection.

The first column select signal line YSW1 is coupled to a gate portion ofthe first diffusion layer DL1 and a left gate portion of the firstcommon diffusion layer CDL1. The second column select signal line YSW2is coupled to a gate portion of the second diffusion layer DL2 and aright gate portion of the first common diffusion layer CDL1. The thirdcolumn select signal line YSW3 is coupled to a gate portion of the thirddiffusion layer DL3 and a left gate portion of the second commondiffusion layer CDL2. The fourth column select signal line YSW4 iscoupled to a gate portion of the fourth diffusion layer DL4 and a rightgate portion of the second common diffusion layer CDL2. The fifth columnselect signal line YSW5 is coupled to a gate portion of the fifthdiffusion layer DL5 and a left gate portion of the third commondiffusion layer CDL3. The sixth column select signal line YSW6 iscoupled to a gate portion of the sixth diffusion layer DL5 and a rightgate portion of the third common diffusion layer CDL3. The seventhcolumn select signal line YSW7 is coupled to a gate portion of theseventh diffusion layer DL7 and a left gate portion of the fourth commondiffusion layer CDL4. The eighth column select signal line YSW8 iscoupled to a gate portion of the eighth diffusion layer DL8 and a rightgate portion of the fourth common diffusion layer CDL4.

The bus line BUS1 is coupled to the respective left areas of the fifthand seventh diffusion layers DL5 and DL7, and the respective right areasof the sixth and eighth diffusion layers DL6 and DL8, as well as therespective center areas of the first and second common diffusion layersCDL1 and CDL2 described above. The dummy bus line DBUS1 is coupled tothe respective left areas of the fifth and third diffusion layers DL1and DL3, and the respective right areas of the second and fourthdiffusion layers DL2 and DL4, as well as the respective center areas ofthe third and fourth common diffusion layers CDL3 and CDL4 describedabove.

The first bit line BL1 is coupled to the right area of the fifthdiffusion layer DL5, and the first and third memory cell arrays MCA1 andMCA3, as well as the left area of the first common diffusion layer CDL1described above. The second bit line BL2 is coupled to the left area ofthe sixth diffusion layer DL6, and the first and third memory cellarrays MCA1 and MCA3, as well as the right area of the first commondiffusion layer CDL1 described above. The third bit line BL3 is coupledto the right area of the seventh diffusion layer DL7, and the first andthird memory cell arrays MCA1 and MCA3, as well as the left area of thesecond common diffusion layer CDL2 described above. The fourth bit lineBL4 is coupled to the left area of the eighth diffusion layer DL8, andthe first and third memory cell arrays MCA1 and MCA3, as well as theright area of the second common diffusion layer CDL2 described above.

The first dummy bit line DBL1 is coupled to the right area of the firstdiffusion layer DL1, and the second and fourth memory cell arrays MCA2and MCA4, as well as the left area of the third common diffusion layerCDL3 described above. The second dummy bit line DBL2 is coupled to theleft area of the second diffusion layer DL2, and the second and fourthmemory cell arrays MCA2 and MCA4, as well as the right area of the thirdcommon diffusion layer CDL3 described above. The third dummy bit lineDBL3 is coupled to the right area of the third diffusion layer DL3, andthe second and fourth memory cell arrays MCA2 and MCA4, as well as theleft area of the fourth common diffusion layer CDL4 described above. Thefourth dummy bit line DBL4 is coupled to the left area of the fourthdiffusion layer DL4, and the second and fourth memory cell arrays MCA2and MCA4, as well as the right area of the fourth common diffusion layerCDL4 described above.

A description will be given of the operation of the semiconductorintegrated circuit device according to the first embodiment of thepresent invention. Even if the semiconductor layout is changed from thatof the related art illustrated in FIG. 4A to that of this embodiment,the semiconductor integrated circuit device functions as the dynamicsemiconductor storage device without any change.

In addition, this embodiment has such an advantage that a total of theareas of various diffusion layers coupled to the bus line BUS1 and thedummy bus line DBUS1 is equal thereto. Accordingly, the bus line BUS1and the dummy bus lien DBUS1 are balanced with each other in thecapacitive load exerted on the respective lines. Thus, according to thisembodiment, saving of the circuit area, resultant saving of themanufacturing costs, and balancing of the capacitive loads on the pairedwirings can be performed at the same time.

Now, attention is paid to antisymmetry in the semiconductor layoutillustrated in FIG. 5A. In the semiconductor layout illustrated in FIG.5A, portions relating to the first and second memory cell arrays MCA1and MCA2 are called “first block”. Likewise, in the semiconductor layoutillustrated in FIG. 5A, portions relating to the third and fourth memorycell arrays MCA3 and MCA4 are called “second block”. That is, the firstblock includes the first and second memory cell arrays MCA1 and MCA2,the first to fourth transfer circuits DQ1 to DQ4, the first to fourthcolumn select signal lines YSW1 to YSW4, the eight transistors DQ1T1,DQ1T2, DQ2T1, DQ2T2, DQ3T1, DQ3T2, DQ4T1, and DQ4T2, and the respectivewirings coupling those components to each other. Likewise, the secondblock includes the third and fourth memory cell arrays MCA3 and MCA4,the fifth to eighth transfer circuits DQ5 to DQ8, the fifth to eighthcolumn select signal lines YSW5 to YSW8, the eight transistors DQ5T1,DQ5T2, DQ6T1, DQ6T2, DQ7T1, DQ7T2, DQ8T1, and DQ8T2, and the respectivewirings coupling those components to each other.

In this situation, the wiring coupling the bus line BUS1 with the firstblock is called “first wiring”. Likewise, the wiring coupling the busline BUS1 with the second block is called “second wiring”. The firstwiring couples the bus line BUS1 with the four transistors DQ1T1, DQ2T1,DQ3T1, and DQ4T1. Since those four transistors are formed in the twocommon diffusion layers CDL1 and CDL2, a total number of the firstwirings is two. The second wiring couples the bus line BUS1 with thefour transistors DQ5T1, DQ6T1, DQ7T1, and DQ8T1. Since those fourtransistors are formed in the respective four diffusion layers DL5 andDL8, a total number of the second wirings is four. Thus, the firstwirings and the second wirings are different in number from each other.

Also, the wiring coupling the dummy bus line DBUS1 with the first blockis called “third wiring”. Likewise, the wiring coupling the bus lineBUS1 with the second block is called “fourth wiring”. The third wiringcouples the dummy bus line DBUS1 with the four transistors DQ1T2, DQ2T2,DQ3T2, and DQ4T2. Since those four transistors are formed in therespective four diffusion layers DL1 to DL4, a total number of the thirdwirings is four. The fourth wiring couples the dummy bus line DBUS1 withthe four transistors DQ5T2, DQ6T2, DQ7T2, and DQ8T2. Since those fourtransistors are formed in the two common diffusion layers CDL3 and CDL4,a total number of the fourth wirings is two. Thus, the third wirings andthe fourth wirings are different in number from each other.

Thus, in the semiconductor layout according to this embodimentillustrated in FIG. 5A, the total number of the first to fourth wiringscoupling the first block and the second block with the bus line bUS1 andthe dummy bus line DBUS1 has an antisymmetric relationship. In otherwords, in the semiconductor integrated circuit device according to thisembodiment, the two blocks having the wirings with the antisymmetricrelationship are combined together into one constituent unit, to therebyeliminate the capacitive unbalance between the complemented bus lines.In this situation, the constituent units are combined togetherinnumerably, thereby enabling a large-capacity storage device to beformed.

Second Embodiment

FIG. 6 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a second embodimentof the present invention. A circuit realized by the semiconductor layoutof FIG. 6 is identical with that in the first embodiment of the presentinvention illustrated in FIG. 5B, and therefore a more detaileddescription thereof will be omitted. The semiconductor layout of FIG. 6is equivalent to the semiconductor layout according to the firstembodiment of the present invention illustrated in FIG. 5A, which ismodified as follows. That is, the positions of the first and secondtransistors DQ3T1 to DQ6T1 and DQ3T2 to DQ6T2 in the respective third tosixth transfer circuits DQ3 to DQ6 are replaced with each other.

As an example, the position replacement of the first and secondtransistors DQ3T1 and DQ3T2 in the third transfer circuit DQ3 will bedescribed in more detail. The first transistor DQ3T1 in the thirdtransfer circuit DQ3 is formed on the left side of the second commondiffusion layer CDL2 in the first embodiment. Likewise, the secondtransistor DQ3T2 in the third transfer circuit DQ3 is formed in thethird diffusion layer DL3 in the first embodiment. However, in thisembodiment, the first transistor DQ3T1 in the third transfer circuit DQ3is formed in the third diffusion layer DL3. Likewise, the secondtransistor DQ3T2 is formed on the left side of the second commondiffusion layer CDL2.

With this change, in this embodiment, as compared with the case in thefirst embodiment according to the present invention, the coupling of oneof the source and the drain of the first transistor DQ3T1 in the thirdtransfer circuit DQ3 with the third bit line BL3 is also changed. Thatis, the third bit line BL3, which is coupled to the left side of thesecond common diffusion layer CDL2 in the first embodiment, is coupledto the right side of the third diffusion layer DL3 in this embodiment.

Likewise, the coupling of one of the source and the drain of the secondtransistor DQ3T2 in the third transfer circuit DQ3 with the third bitline BL3 is also changed. That is, the third dummy bit line DBL3, whichis coupled to the right side of the third diffusion layer DL3 in thefirst embodiment, is coupled to the left side of the second commondiffusion layer in this embodiment.

Furthermore, with those changes, in this embodiment, as compared withthe first embodiment of the present invention, the coupling of the thirdtransfer circuit DQ3 with the bus line BUS1 is also changed. That is,the bus line BUS1, which is coupled to the center portion of the secondcommon diffusion layer CDL2 in the first embodiment of the presentinvention, is coupled to the left side of the third diffusion layer DL3in this embodiment.

Likewise, with those changes, in this embodiment, as compared with thefirst embodiment of the present invention, the coupling of the thirdtransfer circuit DQ3 with the dummy bus line DBUS1 is also changed. Thatis, the dummy bus line DBUS1, which is coupled to the left side of thethird common diffusion layer DL3 in the first embodiment of the presentinvention, is coupled to the center portion of the second commondiffusion layer CDL2 in this embodiment.

Even if the coupling destinations of both ends of the third columnselect signal line YSW3 are replaced with other coupling destinations,the shape and arrangement thereof are not changed.

As with the third transfer circuit DQ3 described above, in thisembodiment, as compared with the first embodiment of the presentinvention, the positions of the first and second transistors DQ4T1 toDQ6T1 and DQ4T2 to DQ6T2 in the respective fourth to sixth transfercircuits DQ4 to DQ6 are changed. Also, with those changes, in thisembodiment, as compared with the first embodiment of the presentinvention, the coupling positions of the fourth to sixth bit lines BL4to BL6, the fourth to sixth dummy bit lines DBL4 to DBL6, the bus lineBUS1, and the dummy bus line DBUS1 are also changed.

The other constituent elements, coupling relationships, and operation ofthe semiconductor integrated circuit device according to this embodimentare identical with those in the first embodiment of the presentinvention, and therefore a more detailed description thereof will beomitted.

According to this embodiment, the following advantages are obtained inaddition to the advantages obtained in the first embodiment of thepresent invention. Referring to FIG. 6, the first and second memory cellarrays MCA1 and MCA2, the first to fourth transfer circuits DQ1 to DQ4,and the wirings pertaining to those constituent elements are called“first configuration unit”. Likewise, the third and fourth memory cellarrays MCA3 and MCA4, the fifth to eighth transfer circuits DQ5 to DQ8,and the wirings pertaining to those constituent elements are called“second configuration unit”. In this situation, the first and secondconstituent units are completely identical in configuration with eachother. Accordingly, the semiconductor layout according to thisembodiment can be expanded to any sizes by merely combining a pluralityof only the first or second constituent units together.

However, from a different viewpoint, the semiconductor integratedcircuit device according to this embodiment also has the sameantisymmetry as that in the first embodiment of the present invention.That is, among the first configuration unit, a portion pertaining to thefour transistors DQ1T1, DQ1T2, DQ2T1, and DQ2T2 is treated as the firstblock. Also, a portion pertaining to the four transistors DQ3T1, DQ3T2,DQ4T1, and DQ4T2 is treated as the second block.

In this case, as the first wiring that couples the bus line BUS1 withthe first block, there is only one wiring coupled to one commondiffusion layer CDL1. Also, as the second wirings that couple the busline BUS1 with the second block, there are two wirings coupled to thetwo diffusion layers DL1 and DL2. Thus, the first wiring and the secondwirings are different in number from each other.

Likewise, as the third wirings that couple the dummy bus line DBUS1 withthe first block, there are two wiring coupled to the two diffusionlayers DL3 and DL4. Also, as the fourth wiring that couples the dummybus line DBUS1 with the second block, there is only one wiring coupledto the one common diffusion layer CDL2. Thus, the third wirings and thefourth wiring are different in number from each other.

Thus, even in the semiconductor layout illustrated in FIG. 6, a totalnumber of the first to fourth wirings that couple the first block andthe second block to the bus line BUS1 and the dummy bus line DBUS1 hasan antisymmetric relationship. Accordingly, even in this embodiment, thesame advantages as those in the first embodiment of the presentinvention are obtained.

Third Embodiment

FIG. 7 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a third embodimentof the present invention. A circuit realized by the semiconductor layoutof FIG. 7 is identical with that in the first embodiment of the presentinvention illustrated in FIG. 5B, and therefore a more detaileddescription thereof will be omitted. The semiconductor layout of FIG. 7is equivalent to the semiconductor layout according to the firstembodiment of the present invention illustrated in FIG. 5A, which ismodified as follows. That is, in FIG. 5A, the two diffusion layersaligned in the longitudinal direction such as the first and thirddiffusion layers DL1 and DL3, or the second and fourth diffusion layersDL2 and DL4, are shared and changed into one common diffusion layer.Also, referring to FIG. 5A, the two common diffusion layers aligned inthe longitudinal direction such as the first and second common diffusionlayers CDL1 and CDL2 are further shared and changed into one commondiffusion layer.

As a first example, a description will be given of the first commondiffusion layer CDL1 in FIG. 7, which is obtained by sharing the firstand fourth diffusion layers DL1 and DL4 in FIG. 5A in detail. The secondtransistor DQ1T2 in the first transfer circuit DQ1, which is formed inthe first diffusion layer DL1 in FIG. 5A, is formed in the first commondiffusion layer CDL1 in FIG. 7. Further, the second transistor DQ3T2 inthe third transfer circuit DQ3, which is formed in the third diffusionlayer DL3 in FIG. SA, is formed in the first common diffusion layer CDL1in FIG. 7.

In this example, the gate portion of the second transistor DQ1T2 in thefirst transfer circuit DQ1 is L-shaped. One end of the L-shaped gateportion is protruded upward from the first common diffusion layer CDL1in FIG. 7. Also, the other end of the L-shaped gate portion is protrudedrightward from the first common diffusion layer CDL1 in FIG. 7.

As a result, an upper right area of the first common diffusion layerCDL1 in FIG. 7 is isolated by the L-shaped gate portion. The upper rightarea operates as one of the source and the drain of the secondtransistor DQ1T2 in the first transfer circuit DQ1, and is coupled withthe first dummy bit line DBL1.

Likewise, the gate portion of the second transistor DQ3T2 in the thirdtransfer circuit DQ3 is also L-shaped. One end of the L-shaped gateportion is protruded downward from the first common diffusion layer CDL1in FIG. 7. Also, the other end of the L-shaped gate portion is protrudedrightward from the first common diffusion layer CDL1 in FIG. 7.

As a result, a lower right area of the first common diffusion layer CDL1in FIG. 7 is isolated by the L-shaped gate portion. The lower right areaoperates as one of the source and the drain of the second transistorDQ3T2 in the third transfer circuit DQ3, and is coupled with the thirddummy bit line DBL3.

The other area of the first common diffusion layer CDL1 operates theother of the source and the drain of the second transistor DQ1T2 in thefirst transfer circuit DQ1. The other area of the first common diffusionlayer CDL1 also operates as the other of the source and the drain of thesecond transistor DQ3T2 in the third transfer circuit DQ3. This area iscalled “common area”. This common area is coupled with the dummy busline DBUS1.

As with the above-described first example, the second and fourthdiffusion layers DL2 and DL4 in FIG. 5A are shared to obtain the thirdcommon diffusion layer CDL3 in FIG. 7. The fifth and seventh diffusionlayers DL5 and DL7 in FIG. 5A are shared to obtain the fourth commondiffusion layer CDL4 in FIG. 7. The sixth and eighth diffusion layersDL6 and DL8 in FIG. 5A are shared to obtain the sixth common diffusionlayer CDL6 in FIG. 7.

The common area of the third common diffusion layer CDL3 is coupled withthe dummy bus line DBUS1 as with the first common diffusion layer CDL1.On the other hand, the respective common areas of the fourth and sixthcommon diffusion layers CDL4 and CDL6 are coupled with the bus lineBUS1.

As a second example, a description will be given of the second commondiffusion layer CDL2 in FIG. 7, which is obtained by sharing the firstand second common diffusion layers CDL1 and CDL2 in FIG. 5A in detail.The first transistors DQ1T1 and DQ2T1 in the respective first and secondtransfer circuits DQ1 and DQ2, which are formed in the first commondiffusion layer CDL1 in FIG. 5A, is formed in the second commondiffusion layer CDL2 in FIG. 7. Further, the first transistors DQ3T1 andDQ4T1 in the respective third and fourth transfer circuit DQ3 and DQ4,which are formed in the second common diffusion layer CDL2 in FIG. 5A,are also formed in the second common diffusion layer CDL2 in FIG. 7.

In this example, the gate portion of the first transistor DQ1T1 in thefirst transfer circuit DQ1 is L-shaped. One end of the L-shaped gateportion is protruded upward from the second common diffusion layer CDL2in FIG. 7. Also, the other end of the L-shaped gate portion is protrudedleftward from the second common diffusion layer CDL2 in FIG. 7.

As a result, an upper left area of the second common diffusion layerCDL2 in FIG. 7 is isolated by the L-shaped gate portion. The upper leftarea operates as one of the source and the drain of the first transistorDQ1T1 in the first transfer circuit DQ1, and is coupled with the firstbit line BL1.

Likewise, the gate portion of the first transistor DQ2T1 in the secondtransfer circuit DQ2 is also L-shaped. One end of the L-shaped gateportion is protruded upward from the second common diffusion layer CDL2in FIG. 7. Also, the other end of the L-shaped gate portion is protrudedrightward from the second common diffusion layer CDL2 in FIG. 7.

As a result, an upper right area of the second common diffusion layerCDL2 in FIG. 7 is isolated by the L-shaped gate portion. The upper rightarea operates as one of the source and the drain of the first transistorDQ2T1 in the second transfer circuit DQ2, and is coupled with the secondbit line BL2.

Likewise, the gate portion of the first transistor DQ3T1 in the thirdtransfer circuit DQ3 is also L-shaped. One end of the L-shaped gateportion is protruded downward from the second common diffusion layerCDL2 in FIG. 7. Also, the other end of the L-shaped gate portion isprotruded leftward from the second common diffusion layer CDL2 in FIG.7.

As a result, a lower left area of the second common diffusion layer CDL2in FIG. 7 is isolated by the L-shaped gate portion. The lower left areaoperates as one of the source and the drain of the first transistorDQ3T1 in the third transfer circuit DQ3, and is coupled with the thirdbit line BL3.

Likewise, the gate portion of the first transistor DQ4T1 in the fourthtransfer circuit DQ4 is also L-shaped. One end of the L-shaped gateportion is protruded downward from the second common diffusion layerCDL2 in FIG. 7. Also, the other end of the L-shaped gate portion isprotruded rightward from the second common diffusion layer CDL2 in FIG.7.

As a result, a lower right area of the second common diffusion layerCDL2 in FIG. 7 is isolated by the L-shaped gate portion. The lower rightarea operates as one of the source and the drain of the first transistorDQ4T1 in the fourth transfer circuit DQ4, and is coupled with the fourthbit line BL4.

The other area of the second common diffusion layer CDL2 operates as theother of the source and the drain of the first transistor DQ1T1 in thefirst transfer circuit DQ1. This area also operates as the others of thesources and the drains of the respective first transistors DQ2T1 toDQ4T1 in the second to fourth transfer circuits DQ2 to DQ4 at the sametime. This area is called “common area.” This common area is coupledwith the bus line BUS1.

As with the above-described second example, the third and fourth commondiffusion layers CDL3 and CDL4 in FIG. 5A are shared to obtain the fifthcommon diffusion layer CDL5 in FIG. 7. The common area of the fifthcommon diffusion layer CDL5 is coupled with the dummy bus line DBUS1instead of the bus line BUS1 coupled to the common area of the secondcommon diffusion layer CDL2.

The other constituent elements, coupling relationships, and operation ofthe semiconductor integrated circuit device according to this embodimentare identical with those in the first embodiment of the presentinvention, and therefore a more detailed description thereof will beomitted.

According to this embodiment, the following advantages are obtained inaddition to the advantages obtained in the first embodiment of thepresent invention. That is, the diffusion layers are shared not only inthe lateral direction but also in the longitudinal direction in FIGS. 5Aand 7, to thereby enable the circuit area to be further reduced. In thiscase, the L-shaped transistor is introduced to ensure the operation asthe circuit.

The semiconductor integrated circuit device according to this embodimenthas the antisymmetry as with the first embodiment of the presentinvention. Similarly, in this embodiment, it is assumed that the firstblock and the second block are defined in the same manner as those inthe first embodiment of the present invention. In this example, only onefirst wiring that couples the bus line BUS1 with the first block isprovided, which is coupled to one common diffusion layer CDL2. Also,only two second wirings that couple the bus line BUS1 with the secondblock are provided, which are coupled to the two common diffusion layersCDL4 and CDL6. Further, only two third wirings that couple the dummy busline DBUS1 with the first block are provided which are coupled to thetwo common diffusion layers CDL1 and CDL3. Also, only one fourth wiringthat couples the dummy bus line DBUS1 with the second block is providedwhich is coupled to one common diffusion layer CDL5.

Thus, the first wirings and the second wirings are different in numberfrom each other. Likewise, the third wirings and the fourth wirings aredifferent in number from each other. That is, in the semiconductorlayout according to this embodiment illustrated in FIG. 7, a totalnumber of the first to fourth wirings that couple the first block andthe second block with the bus line BUST and the dummy bus line DBUS1 hasan antisymmetric relationship. Accordingly, even this embodiment obtainsthe same advantages as those in the first embodiment of the presentinvention.

Fourth Embodiment

FIG. 8 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a fourth embodimentof the present invention. A circuit realized by the semiconductor layoutof FIG. 8 is identical with that in the first embodiment of the presentinvention illustrated in FIG. 5B, and therefore a more detaileddescription thereof will be omitted. The first to third embodiments ofthe present invention deal with the sense amplifier of a so-called openbit line system. On the other hand, this embodiment deals with a senseamplifier of a so-called folding bit line system. Accordingly, in thefirst to third embodiments of the present invention, two bit lines ordummy bit lines in total at a maximum are coupled to one memory cellarray. On the other hand, in this embodiment, four bit lines or dummybit lines in total at a maximum are coupled to one memory cell array.Also, in the first to third embodiments of the present invention, twoadjacent memory cell arrays are arranged between two diffusion layers ortwo common diffusion layers. On the other hand, in this embodiment, thenumber of memory cell arrays arranged between the two common diffusionlayers is one.

The semiconductor layout according to this embodiment illustrated inFIG. 8 is equivalent to the semiconductor layout according to the secondembodiment of the present invention illustrated in FIG. 7, which ismodified as follows. That is, as described above, the adjacent secondand third memory cell arrays MCA2 and MCA3 in FIG. 7 are replaced withone memory cell array MCA2 in FIG. 8. With this change, it is assumedthat the fourth memory cell array MCA4 in FIG. 7 is the third memorycell array MCA3 in FIG. 8. Further, the coupling of the first to fourthbit lines BL1 to BL4 and the first to fourth dummy bit lines DBL1 toDBL4 with the respective memory cell arrays is changed. In thissituation, the coupling relationships of the first to fourth bit linesBL1 to BL4, the first to fourth dummy bit lines DBL1 to DBL4, the busline BUS1, and the dummy bus line DBUS1 with the respective commondiffusion layers are identical with those in the third embodiment of thepresent invention illustrated in FIG. 7.

As a first example, a description will be given of the couplingdestinations of the other ends of the respective wirings having one endscoupled to the first to third common diffusion layers CDL1 to CDL3 indetail. The other end of the first bit line BL1 having one end coupledto the upper left area of the second common diffusion layer CDL2 iscoupled to the first memory cell array MCA1. The other end of the secondbit line BL2 having one end coupled to the upper right area of thesecond common diffusion layer CDL2 is coupled to the second memory cellarray MCA2. The other end of the third bit line BL3 having one endcoupled to the lower left area of the second common diffusion layer CDL2is coupled to the first memory cell array MCA1. The other end of thefourth bit line BL4 having one end coupled to the lower right area ofthe second common diffusion layer CDL2 is coupled to the second memorycell array MCA2.

The other end of the first dummy bit line DBL1 having one end coupled tothe upper right area of the first common diffusion layer CDL1 is coupledto the first memory cell array MCA1. The other end of the second dummybit line DBL2 having one end coupled to the upper left area of the thirdcommon diffusion layer CDL3 is coupled to the second memory cell arrayMCA2. The other end of the third dummy bit line DBL3 having one endcoupled to the upper right area of the first common diffusion layer CDL1is coupled to the first memory cell array MCA1. The other end of thefourth dummy bit line DBL4 having one end coupled to the lower left areaof the third common diffusion layer CDL3 is coupled to the second memorycell array MCA2.

The common area of the second common diffusion layer CDL2 is coupledwith the bus line BUS1. The respective common areas of the first andthird common diffusion layers CDL1 and CDL3 are coupled with the dummybus line DBUS1.

As a second example, a description will be given of the couplingdestinations of the other ends of the respective wirings having one endscoupled to the fourth to sixth common diffusion layers CDL4 to CDL6 indetail. The other end of the first dummy bit line DBL1 having one endcoupled to the upper left area of the fifth common diffusion layer CDL5is coupled to the second memory cell array MCA2. The other end of thesecond dummy bit line DBL2 having one end coupled to the upper rightarea of the fifth common diffusion layer CDL5 is coupled to the thirdmemory cell array MCA3. The other end of the third dummy bit line DBL3having one end coupled to the lower left area of the fifth commondiffusion layer CDL5 is coupled to the second memory cell array MCA2.The other end of the fourth dummy bit line DBL4 having one end coupledto the lower right area of the fifth common diffusion layer CDL5 iscoupled to the third memory cell array MCA3.

The other end of the first bit line BL1 having one end coupled to theupper right area of the fourth common diffusion layer CDL4 is coupled tothe second memory cell array MCA2. The other end of the second bit lineBL2 having one end coupled to the upper left area of the sixth commondiffusion layer CDL6 is coupled to the third memory cell array MCA3. Theother end of the third bit line BL3 having one end coupled to the lowerright area of the fourth common diffusion layer CDL4 is coupled to thesecond memory cell array MCA2. The other end of the fourth bit line BL4having one end coupled to the lower left area of the sixth commondiffusion layer CDL6 is coupled to the third memory cell array MCA3.

The common area of the fifth common diffusion layer CDL5 is coupled withthe dummy bus line DBUS1. The respective common areas of the fourth andsixth common diffusion layers CDL4 and CDL6 are coupled with the busline BUS1.

In FIG. 8, the coupling relationships of the first memory cell arrayMCA1 with the first to fourth dummy bit lines DBL1 to DBL4 are notomitted. However, this configuration absolutely represents an example ofthe end of the semiconductor layout, and does not limit the presentinvention.

The other constituent elements, coupling relationships, and operation ofthe semiconductor integrated circuit device according to this embodimentare identical with those in the third embodiment of the presentinvention, and therefore a more detailed description thereof will beomitted.

In the semiconductor layout according to this embodiment, the secondmemory cell array MCA2 and the first to third common diffusion layersCDL1 to CDL3 are called “first configuration unit”. Also, the thirdmemory cell array MCA3 and the fourth to sixth common diffusion layersCDL4 to CDL6 are called “second configuration unit”. The first andsecond configuration units are alternately arranged in the lateraldirection of FIG. 8, to thereby balance the capacitive loads of the busline BUST and the dummy bus line DBUS1 which are the wiring pair.

According to this embodiment, not only when the sense amplifier of theopen bit line system is used according to the first to third embodimentsof the present invention, but also when the sense amplifier of thefolding bit line system is used, both of a reduction in the circuitarea, and the balance of the capacitive loads between the wiring paircan be performed.

As in the third embodiment of the present invention, the semiconductorintegrated circuit device according to this embodiment also has theantisymmetry. However, this embodiment is different from the thirdembodiment of the present invention in that the memory cell arrayincluded in the first block is configured by the first memory cell arrayMCA1 and a part of the second memory cell array MCA2, and the memorycell array included in the second block is configured by a part of thesecond memory cell array MCA2, and the third memory cell array MCA3. Theother features and advantages pertaining to the antisymmetry in thesemiconductor integrated circuit device according to this embodiment areidentical with those in the third embodiment of the present invention,and therefore a more detailed description thereof will be omitted.

Fifth Embodiment

FIG. 9 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a fifth embodimentof the present invention. A circuit realized by the semiconductor layoutof FIG. 9 is identical with that in the first embodiment of the presentinvention illustrated in FIG. 5B, and therefore a more detaileddescription thereof will be omitted. The semiconductor layout of FIG. 9is equivalent to the first and second configuration units aligned in thelateral direction of FIG. 8 in the fourth embodiment of the presentinvention, which is realigned in the longitudinal direction. That is,the first and second memory cell arrays MCA1 and MCA2 according to thisembodiment illustrated in FIG. 9 are equivalent to the first and secondmemory cell arrays MCA1 and MCA2 according to the fourth embodiment ofthe present invention illustrated in FIG. 8. Also, the first to thirdcommon diffusion layers according to this embodiment illustrated in FIG.9 are equivalent to the first to third common diffusion layers accordingto the fourth embodiment of the present invention illustrated in FIG. 8.Likewise, the third and fourth memory cell arrays MCA3 and MCA4 in FIG.9 are equivalent to the second and third memory cell arrays MCA2 andMCA3 according to the fourth embodiment of the present inventionillustrated in FIG. 8. The fourth to sixth common diffusion layersaccording to this embodiment illustrated in FIG. 9 are equivalent to thefourth to sixth common diffusion layers according to the fourthembodiment of the present invention illustrated in FIG. 8. Further, thebus line BUS1 according to this embodiment illustrated in FIG. 9 is alsocoupled to the second, fourth, and sixth common diffusion layers CDL2,CDL4, and CDL6 as in the fourth embodiment of the present inventionillustrated in FIG. 8. Also, the dummy bus line DBUS1 according to thisembodiment illustrated in FIG. 9 is also coupled to the first, third,and fifth common diffusion layers CDL1, CDL3, and CDL5 as in the fourthembodiment of the present invention illustrated in FIG. 8.

In FIG. 9, the coupling relationships of the first and third memory cellarrays MCA1 and MCA3 with the first to fourth dummy bit lines DBL1 toDBL4 are not omitted. However, this configuration absolutely representsan example of the end of the semiconductor layout, and does not limitthe present invention.

The other constituent elements, coupling relationships, and operation ofthe semiconductor integrated circuit device according to this embodimentare identical with those in the fourth embodiment of the presentinvention, and therefore a more detailed description thereof will beomitted.

According to this embodiment, the same advantages as those in the fourthembodiment of the present invention are obtained. The first and secondconfiguration units are alternately arranged in the lateral direction inFIG. 8 in the fourth embodiment of the present invention, butalternately arranged in the longitudinal direction of FIG. 9 in thisembodiment.

Accordingly, the semiconductor integrated circuit device according tothis embodiment also has the antisymmetry as in the fourth embodiment ofthe present invention. This embodiment is different from the fourthembodiment of the present invention in that the memory cell arraysincluded in the first block are the first memory cell array MCA1 and apart of the second memory cell array MCA2, and the memory cell arraysincluded in the second block are the third memory cell array MCA3 and apart of the fourth memory cell array MCA4. The other features andadvantages pertaining to the antisymmetry in the semiconductorintegrated circuit device according to this embodiment are identicalwith those in the fourth embodiment of the present invention, andtherefore a more detailed description will be omitted.

Sixth Embodiment

FIG. 10 is a plan view illustrating a semiconductor layout of asemiconductor integrated circuit device according to a sixth embodimentof the present invention. A circuit realized by the semiconductor layoutof FIG. 10 is identical with a left half of the first embodiment of thepresent invention illustrated in FIG. 5B, that is, a portion pertainingto the first to fourth transfer circuits DQ1 to DQ4, and therefore amore detailed description thereof will be omitted.

The semiconductor layout of FIG. 10 includes the first and second memorycell arrays MCA1 and MCA2, the first and second common diffusion layersCDL1 and CDL2, the first to fourth bit lines BL1 to BL4, the first tofourth dummy bit lines DBL1 to DBL4, the first to fourth column selectsignal lines YSW1 to YSW4, the bus line BUS1, and the dummy bus lineDBUS1.

The first common diffusion layer CDL1 is formed with the firsttransistors DQ1T1 to DQ4T1 of the respective first to fourth transfercircuits DQ1 to DQ4. In this example, the respective gate portions ofthe first transistors DQ1T1 to DQ4T1 in the respective first to fourthtransfer circuits DQ1 to DQ4 are L-shaped.

The L-shaped gate portion of the first transistor DQ1T1 in the firsttransfer circuit DQ1 has one end protruded upward from the first commondiffusion layer CDL1 in FIG. 10. Also, the L-shaped gate portion has theother end protruded leftward, likewise. As a result, the upper left areaof the first common diffusion layer CDL1 in FIG. 10 is isolated by theL-shaped portion. The upper left area operates as one of the source andthe drain of the first transistor DQ1T1 in the first transfer circuitDQ1, and is coupled with the first bit line BL1. The first bit line BL1is also coupled to the first memory cell array MCA1.

The L-shaped gate portion of the first transistor DQ2T1 in the secondtransfer circuit DQ2 has one end protruded upward from the first commondiffusion layer CDL1 in FIG. 10. Also, the L-shaped gate portion has theother end protruded rightward, likewise. As a result, the upper rightarea of the first common diffusion layer CDL1 in FIG. 10 is isolated bythe L-shaped portion. The upper right area operates as one of the sourceand the drain of the first transistor DQ2T1 in the second transfercircuit DQ2, and is coupled with the second bit line BL2. The second bitline BL2 is also coupled to the second memory cell array MCA2.

The L-shaped gate portion of the first transistor DQ3T1 in the thirdtransfer circuit DQ3 has one end protruded downward from the firstcommon diffusion layer CDL1 in FIG. 10. Also, the L-shaped gate portionhas the other end protruded leftward, likewise. As a result, the lowerleft area of the first common diffusion layer CDL1 in FIG. 10 isisolated by the L-shaped portion. The lower left area operates as one ofthe source and the drain of the first transistor DQ3T1 in the thirdtransfer circuit DQ3, and is coupled with the third bit line BL3. Thethird bit line BL3 is also coupled to the first memory cell array MCA1.

The L-shaped gate portion of the first transistor DQ4T1 in the fourthtransfer circuit DQ4 has one end protruded downward from the firstcommon diffusion layer CDL1 in FIG. 10. Also, the L-shaped gate portionhas the other end protruded rightward, likewise. As a result, the lowerright area of the first common diffusion layer CDL1 in FIG. 10 isisolated by the L-shaped portion. The lower right area operates as oneof the source and the drain of the first transistor DQ4T1 in the fourthtransfer circuit DQ4, and is coupled with the fourth bit line BL4. Thefourth bit line BL4 is also coupled to the second memory cell arrayMCA2.

The other area of the first common diffusion layer CDL1 are shared asthe others of the sources and the drains of the respective firsttransistors DQ1T1 to DQ4T1 in the respective first to fourth transfercircuits DQ1 to DQ4, and operates. This area is called “common area”.This common area is coupled with the bus line BUS1.

Likewise, the L-shaped gate portion of the second transistor DQ1T2 inthe first transfer circuit DQ1 has one end protruded upward from thesecond common diffusion layer CDL2 in FIG. 10. Also, the L-shaped gateportion has the other end protruded rightward, likewise. As a result,the upper right area of the second common diffusion layer CDL2 in FIG.10 is isolated by the L-shaped portion. The upper right area operates asone of the source and the drain of the second transistor DQ1T2 in thefirst transfer circuit DQ1, and is coupled with the first dummy bit lineDBL1. The first dummy bit line DBL1 is also coupled to the first memorycell array MCA1.

The L-shaped gate portion of the second transistor DQ2T2 in the secondtransfer circuit DQ2 has one end protruded upward from the second commondiffusion layer CDL2 in FIG. 10. Also, the L-shaped gate portion has theother end protruded leftward, likewise. As a result, the upper left areaof the second common diffusion layer CDL2 in FIG. 10 is isolated by theL-shaped portion. The upper left area operates as one of the source andthe drain of the second transistor DQ1T2 in the second transfer circuitDQ2, and is coupled with the second dummy bit line DBL2. The seconddummy bit line DBL2 is also coupled to the second memory cell arrayMCA2.

The L-shaped gate portion of the second transistor DQ3T2 in the thirdtransfer circuit DQ3 has one end protruded downward from the secondcommon diffusion layer CDL2 in FIG. 10. Also, the L-shaped gate portionhas the other end protruded rightward, likewise. As a result, the lowerright area of the second common diffusion layer CDL2 in FIG. 10 isisolated by the L-shaped portion. The lower right area operates as oneof the source and the drain of the second transistor DQ3T2 in the thirdtransfer circuit DQ3, and is coupled with the third dummy bit line DBL3.The third dummy bit line DBL3 is also coupled to the first memory cellarray MCA1.

The L-shaped gate portion of the second transistor DQ4T2 in the fourthtransfer circuit DQ4 has one end protruded downward from the secondcommon diffusion layer CDL2 in FIG. 10. Also, the L-shaped gate portionhas the other end protruded leftward, likewise. As a result, the lowerleft area of the second common diffusion layer CDL2 in FIG. 10 isisolated by the L-shaped portion. The lower right area operates as oneof the source and the drain of the second transistor DQ4T2 in the fourthtransfer circuit DQ4, and is coupled with the fourth dummy bit lineDBL4. The fourth dummy bit line DBL4 is also coupled to the secondmemory cell array MCA2.

The other area of the second common diffusion layer CDL2 are shared asthe others of the sources and the drains of the respective secondtransistors DQ1T2 to DQ4T2 in the respective first to fourth transfercircuits DQ1 to DQ4, and operates. This area is called “common area”.This common area is coupled with the dummy bus line DBUS1.

The first column select signal line YSW1 couples the upward protrudedportions of the respective L-shaped gate portions of the first andsecond transistors DQ1T1 and DQ1T2 in the first transfer circuit DQ1with each other. The second column select signal line YSW2 couples theupward protruded portions of the respective L-shaped gate portions ofthe first and second transistors DQ2T1 and DQ2T2 in the second transfercircuit DQ2 with each other. The third column select signal line YSW3couples the downward protruded portions of the respective L-shaped gateportions of the first and second transistors DQ3T1 and DQ3T2 in thethird transfer circuit DQ3 with each other. The fourth column selectsignal line YSW4 couples the downward protruded portions of therespective L-shaped gate portions of the first and second transistorsDQ4T1 and DQ4T2 in the fourth transfer circuit DQ4 with each other.

In FIG. 10, the first memory cell array MCA1 is not coupled with thesecond bit line BL2, the second dummy bit line DBL2, the fourth bit lineBL4, and the fourth dummy bit line DBL4. However, this configurationabsolutely represents an example in which the first memory cell arrayMCA1 is arranged on the end, and does not limit the present invention.

According to the semiconductor layout of this embodiment, the circuitarea can be further reduced as compared with the first to fifthembodiments of the present invention. Further, according to thesemiconductor layout of this embodiment, the subject configuration unitsof the semiconductor integrated circuit device are reduced by half. Thatis, the first and second common diffusion layers CDL1 and CDL2, and oneof the first and second memory cell arrays MCA1 and MCA2 are regarded asthe configuration unit. When the configuration units are merely alignedin the lateral direction in FIG. 10, the capacitive loads of the busline BUS1 and the dummy bus line DBUS1 which are the wiring pair arebalanced with each other.

On the other hand, in this embodiment, as compared with the first tofifth embodiments of the present invention, variations of the lengths ofthe respective bit lines and the respective dummy bit lines arenoticeable. However, the sizes of the respective memory cell arrays inthe lateral direction in FIG. 10 are actually larger than the respectivecommon diffusion layers, and therefore those variations fall within anerror range.

The semiconductor layout according to the respective embodiments of thepresent invention can be freely combined together if there is notechnical discrepancy.

What is claimed is:
 1. A semiconductor integrated circuit device,comprising: a first and a second bus line making a bus line pair; and aplurality of circuit units, each of the circuit units including: a firsttransistor; a second transistor; and a third and a fourth transistorsharing a source or a drain, wherein the circuit units includes a firstand a second circuit unit arranged in a first direction, wherein one ofa source and a drain of the first transistor of the first circuit unitand one of a source and a drain of the second transistor of the firstcircuit unit are coupled to the first bus line, wherein the source orthe drain shared by the third and the fourth transistor of the firstcircuit unit is coupled to the second bus line, wherein one of a sourceand a drain of the first transistor of the second circuit unit and oneof a source and a drain of the second transistor of the second circuitunit are coupled to the second bus line, and wherein the source or thedrain shared by the third and the fourth transistor of the secondcircuit unit is coupled to the first bus line.
 2. The semiconductorintegrated circuit device according to claim 1, wherein the first, thethird, the fourth and the second transistor are arranged in this orderin the first direction.
 3. The semiconductor integrated circuit deviceaccording to claim 1, wherein a gate of the first transistor is coupledto a gate of the third transistor, and a gate of the second transistoris coupled to a gate of the fourth transistor.
 4. The semiconductorintegrated circuit device according to claim 1, wherein each of thecircuit units further comprises fifth to eighth transistors, wherein oneof a source and a drain of the fifth transistor is shared with the oneof the source and the drain of the first transistor, wherein one of asource and a drain of the sixth transistor is shared with the one of asource and a drain of the second transistor, and wherein the seventh andthe eighth transistor sharing a source or a drain, the source or thedrain shared by the seventh and the eighth transistor is shared with thesource or the drain shared by the third and the fourth transistor. 5.The semiconductor integrated circuit device according to claim 1,further comprises a first bit line pair and a second bit line pair,wherein one of the first bit line pair is coupled to the other of thesource and the drain of the first transistor, the other of the first bitline pair is coupled to the other of the source and the drain of thethird transistor, and wherein one of the second bit line pair is coupledto the other of the source and the drain of the second transistor, theother of the second bit line pair is coupled to the other of the sourceand the drain of the fourth transistor.
 6. The semiconductor integratedcircuit device according to claim 5, further comprises a plurality ofmemory cell arrays including a plurality of memory cells, wherein thememory cell arrays and the circuit units are alternately arranged in thefirst direction, and wherein the memory cells coupled to the one of thefirst bit line pair and the memory cells coupled to the other of thefirst bit line pair are arranged in respectively different memory cellarrays.
 7. The semiconductor integrated circuit device according toclaim 5, further comprises a plurality of memory cell arrays including aplurality of memory cells, wherein the memory cell arrays and thecircuit units are alternately arranged in the first direction, andwherein the memory cells coupled to the one of the first bit line pairand the memory cells coupled to the other of the first bit line pair arearranged in the same memory cell array.
 8. A semiconductor integratedcircuit device, comprising: a first and a second bus line making a busline pair; and a plurality of circuit units, each of the circuit unitsincluding: a first transistor having a first diffusion region as one ofa source and a drain, a second transistor having a second diffusionregion as one of a source and a drain, and a third and a fourthtransistor sharing a third diffusion region as a common source or acommon drain, and wherein the first, the second, the third and thefourth transistor are arranged in a first direction, wherein the circuitunits includes a first and a second circuit unit arranged in the firstdirection, wherein the first diffusion region of the first circuit unitand the second diffusion region of the first circuit unit are coupled tothe first bus line, wherein the third diffusion region of the firstcircuit unit is coupled to the second bus line, wherein the firstdiffusion region of the second circuit unit and the second diffusionregion of the second circuit unit are coupled to the second bus line,and wherein the third diffusion region of the second circuit unit iscoupled to the first bus line.
 9. The semiconductor integrated circuitdevice according to claim 8, wherein each of the circuit units furthercomprises fifth to eighth transistors, wherein the fifth transistorshares the first diffusion region with the first transistor, wherein thesixth transistor shares with the second diffusion region with the secondtransistor, and wherein the seventh and the eighth transistor shares thethird diffusion region with the third and the fourth transistor.